155 #define RTE_ETHDEV_HAS_LRO_SUPPORT
158 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
159 #define RTE_ETHDEV_DEBUG_RX
160 #define RTE_ETHDEV_DEBUG_TX
163 #include <rte_compat.h>
171 #include <rte_config.h>
176 #include "rte_dev_info.h"
178 extern int rte_eth_dev_logtype;
180 #define RTE_ETHDEV_LOG(level, ...) \
181 rte_log(RTE_LOG_ ## level, rte_eth_dev_logtype, "" __VA_ARGS__)
246 #define RTE_ETH_FOREACH_MATCHING_DEV(id, devargs, iter) \
247 for (rte_eth_iterator_init(iter, devargs), \
248 id = rte_eth_iterator_next(iter); \
249 id != RTE_MAX_ETHPORTS; \
250 id = rte_eth_iterator_next(iter))
290 #define RTE_ETH_LINK_SPEED_AUTONEG 0
291 #define ETH_LINK_SPEED_AUTONEG RTE_ETH_LINK_SPEED_AUTONEG
292 #define RTE_ETH_LINK_SPEED_FIXED RTE_BIT32(0)
293 #define ETH_LINK_SPEED_FIXED RTE_ETH_LINK_SPEED_FIXED
294 #define RTE_ETH_LINK_SPEED_10M_HD RTE_BIT32(1)
295 #define ETH_LINK_SPEED_10M_HD RTE_ETH_LINK_SPEED_10M_HD
296 #define RTE_ETH_LINK_SPEED_10M RTE_BIT32(2)
297 #define ETH_LINK_SPEED_10M RTE_ETH_LINK_SPEED_10M
298 #define RTE_ETH_LINK_SPEED_100M_HD RTE_BIT32(3)
299 #define ETH_LINK_SPEED_100M_HD RTE_ETH_LINK_SPEED_100M_HD
300 #define RTE_ETH_LINK_SPEED_100M RTE_BIT32(4)
301 #define ETH_LINK_SPEED_100M RTE_ETH_LINK_SPEED_100M
302 #define RTE_ETH_LINK_SPEED_1G RTE_BIT32(5)
303 #define ETH_LINK_SPEED_1G RTE_ETH_LINK_SPEED_1G
304 #define RTE_ETH_LINK_SPEED_2_5G RTE_BIT32(6)
305 #define ETH_LINK_SPEED_2_5G RTE_ETH_LINK_SPEED_2_5G
306 #define RTE_ETH_LINK_SPEED_5G RTE_BIT32(7)
307 #define ETH_LINK_SPEED_5G RTE_ETH_LINK_SPEED_5G
308 #define RTE_ETH_LINK_SPEED_10G RTE_BIT32(8)
309 #define ETH_LINK_SPEED_10G RTE_ETH_LINK_SPEED_10G
310 #define RTE_ETH_LINK_SPEED_20G RTE_BIT32(9)
311 #define ETH_LINK_SPEED_20G RTE_ETH_LINK_SPEED_20G
312 #define RTE_ETH_LINK_SPEED_25G RTE_BIT32(10)
313 #define ETH_LINK_SPEED_25G RTE_ETH_LINK_SPEED_25G
314 #define RTE_ETH_LINK_SPEED_40G RTE_BIT32(11)
315 #define ETH_LINK_SPEED_40G RTE_ETH_LINK_SPEED_40G
316 #define RTE_ETH_LINK_SPEED_50G RTE_BIT32(12)
317 #define ETH_LINK_SPEED_50G RTE_ETH_LINK_SPEED_50G
318 #define RTE_ETH_LINK_SPEED_56G RTE_BIT32(13)
319 #define ETH_LINK_SPEED_56G RTE_ETH_LINK_SPEED_56G
320 #define RTE_ETH_LINK_SPEED_100G RTE_BIT32(14)
321 #define ETH_LINK_SPEED_100G RTE_ETH_LINK_SPEED_100G
322 #define RTE_ETH_LINK_SPEED_200G RTE_BIT32(15)
323 #define ETH_LINK_SPEED_200G RTE_ETH_LINK_SPEED_200G
329 #define RTE_ETH_SPEED_NUM_NONE 0
330 #define ETH_SPEED_NUM_NONE RTE_ETH_SPEED_NUM_NONE
331 #define RTE_ETH_SPEED_NUM_10M 10
332 #define ETH_SPEED_NUM_10M RTE_ETH_SPEED_NUM_10M
333 #define RTE_ETH_SPEED_NUM_100M 100
334 #define ETH_SPEED_NUM_100M RTE_ETH_SPEED_NUM_100M
335 #define RTE_ETH_SPEED_NUM_1G 1000
336 #define ETH_SPEED_NUM_1G RTE_ETH_SPEED_NUM_1G
337 #define RTE_ETH_SPEED_NUM_2_5G 2500
338 #define ETH_SPEED_NUM_2_5G RTE_ETH_SPEED_NUM_2_5G
339 #define RTE_ETH_SPEED_NUM_5G 5000
340 #define ETH_SPEED_NUM_5G RTE_ETH_SPEED_NUM_5G
341 #define RTE_ETH_SPEED_NUM_10G 10000
342 #define ETH_SPEED_NUM_10G RTE_ETH_SPEED_NUM_10G
343 #define RTE_ETH_SPEED_NUM_20G 20000
344 #define ETH_SPEED_NUM_20G RTE_ETH_SPEED_NUM_20G
345 #define RTE_ETH_SPEED_NUM_25G 25000
346 #define ETH_SPEED_NUM_25G RTE_ETH_SPEED_NUM_25G
347 #define RTE_ETH_SPEED_NUM_40G 40000
348 #define ETH_SPEED_NUM_40G RTE_ETH_SPEED_NUM_40G
349 #define RTE_ETH_SPEED_NUM_50G 50000
350 #define ETH_SPEED_NUM_50G RTE_ETH_SPEED_NUM_50G
351 #define RTE_ETH_SPEED_NUM_56G 56000
352 #define ETH_SPEED_NUM_56G RTE_ETH_SPEED_NUM_56G
353 #define RTE_ETH_SPEED_NUM_100G 100000
354 #define ETH_SPEED_NUM_100G RTE_ETH_SPEED_NUM_100G
355 #define RTE_ETH_SPEED_NUM_200G 200000
356 #define ETH_SPEED_NUM_200G RTE_ETH_SPEED_NUM_200G
357 #define RTE_ETH_SPEED_NUM_UNKNOWN UINT32_MAX
358 #define ETH_SPEED_NUM_UNKNOWN RTE_ETH_SPEED_NUM_UNKNOWN
375 #define RTE_ETH_LINK_HALF_DUPLEX 0
376 #define ETH_LINK_HALF_DUPLEX RTE_ETH_LINK_HALF_DUPLEX
377 #define RTE_ETH_LINK_FULL_DUPLEX 1
378 #define ETH_LINK_FULL_DUPLEX RTE_ETH_LINK_FULL_DUPLEX
379 #define RTE_ETH_LINK_DOWN 0
380 #define ETH_LINK_DOWN RTE_ETH_LINK_DOWN
381 #define RTE_ETH_LINK_UP 1
382 #define ETH_LINK_UP RTE_ETH_LINK_UP
383 #define RTE_ETH_LINK_FIXED 0
384 #define ETH_LINK_FIXED RTE_ETH_LINK_FIXED
385 #define RTE_ETH_LINK_AUTONEG 1
386 #define ETH_LINK_AUTONEG RTE_ETH_LINK_AUTONEG
387 #define RTE_ETH_LINK_MAX_STR_LEN 40
394 struct rte_eth_thresh {
403 #define RTE_ETH_MQ_RX_RSS_FLAG RTE_BIT32(0)
404 #define ETH_MQ_RX_RSS_FLAG RTE_ETH_MQ_RX_RSS_FLAG
405 #define RTE_ETH_MQ_RX_DCB_FLAG RTE_BIT32(1)
406 #define ETH_MQ_RX_DCB_FLAG RTE_ETH_MQ_RX_DCB_FLAG
407 #define RTE_ETH_MQ_RX_VMDQ_FLAG RTE_BIT32(2)
408 #define ETH_MQ_RX_VMDQ_FLAG RTE_ETH_MQ_RX_VMDQ_FLAG
437 #define ETH_MQ_RX_NONE RTE_ETH_MQ_RX_NONE
438 #define ETH_MQ_RX_RSS RTE_ETH_MQ_RX_RSS
439 #define ETH_MQ_RX_DCB RTE_ETH_MQ_RX_DCB
440 #define ETH_MQ_RX_DCB_RSS RTE_ETH_MQ_RX_DCB_RSS
441 #define ETH_MQ_RX_VMDQ_ONLY RTE_ETH_MQ_RX_VMDQ_ONLY
442 #define ETH_MQ_RX_VMDQ_RSS RTE_ETH_MQ_RX_VMDQ_RSS
443 #define ETH_MQ_RX_VMDQ_DCB RTE_ETH_MQ_RX_VMDQ_DCB
444 #define ETH_MQ_RX_VMDQ_DCB_RSS RTE_ETH_MQ_RX_VMDQ_DCB_RSS
456 #define ETH_MQ_TX_NONE RTE_ETH_MQ_TX_NONE
457 #define ETH_MQ_TX_DCB RTE_ETH_MQ_TX_DCB
458 #define ETH_MQ_TX_VMDQ_DCB RTE_ETH_MQ_TX_VMDQ_DCB
459 #define ETH_MQ_TX_VMDQ_ONLY RTE_ETH_MQ_TX_VMDQ_ONLY
487 RTE_ETH_VLAN_TYPE_UNKNOWN = 0,
490 RTE_ETH_VLAN_TYPE_MAX,
493 #define ETH_VLAN_TYPE_UNKNOWN RTE_ETH_VLAN_TYPE_UNKNOWN
494 #define ETH_VLAN_TYPE_INNER RTE_ETH_VLAN_TYPE_INNER
495 #define ETH_VLAN_TYPE_OUTER RTE_ETH_VLAN_TYPE_OUTER
496 #define ETH_VLAN_TYPE_MAX RTE_ETH_VLAN_TYPE_MAX
537 #define RTE_ETH_FLOW_UNKNOWN 0
538 #define RTE_ETH_FLOW_RAW 1
539 #define RTE_ETH_FLOW_IPV4 2
540 #define RTE_ETH_FLOW_FRAG_IPV4 3
541 #define RTE_ETH_FLOW_NONFRAG_IPV4_TCP 4
542 #define RTE_ETH_FLOW_NONFRAG_IPV4_UDP 5
543 #define RTE_ETH_FLOW_NONFRAG_IPV4_SCTP 6
544 #define RTE_ETH_FLOW_NONFRAG_IPV4_OTHER 7
545 #define RTE_ETH_FLOW_IPV6 8
546 #define RTE_ETH_FLOW_FRAG_IPV6 9
547 #define RTE_ETH_FLOW_NONFRAG_IPV6_TCP 10
548 #define RTE_ETH_FLOW_NONFRAG_IPV6_UDP 11
549 #define RTE_ETH_FLOW_NONFRAG_IPV6_SCTP 12
550 #define RTE_ETH_FLOW_NONFRAG_IPV6_OTHER 13
551 #define RTE_ETH_FLOW_L2_PAYLOAD 14
552 #define RTE_ETH_FLOW_IPV6_EX 15
553 #define RTE_ETH_FLOW_IPV6_TCP_EX 16
554 #define RTE_ETH_FLOW_IPV6_UDP_EX 17
556 #define RTE_ETH_FLOW_PORT 18
557 #define RTE_ETH_FLOW_VXLAN 19
558 #define RTE_ETH_FLOW_GENEVE 20
559 #define RTE_ETH_FLOW_NVGRE 21
560 #define RTE_ETH_FLOW_VXLAN_GPE 22
561 #define RTE_ETH_FLOW_GTPU 23
562 #define RTE_ETH_FLOW_MAX 24
568 #define RTE_ETH_RSS_IPV4 RTE_BIT64(2)
569 #define ETH_RSS_IPV4 RTE_ETH_RSS_IPV4
570 #define RTE_ETH_RSS_FRAG_IPV4 RTE_BIT64(3)
571 #define ETH_RSS_FRAG_IPV4 RTE_ETH_RSS_FRAG_IPV4
572 #define RTE_ETH_RSS_NONFRAG_IPV4_TCP RTE_BIT64(4)
573 #define ETH_RSS_NONFRAG_IPV4_TCP RTE_ETH_RSS_NONFRAG_IPV4_TCP
574 #define RTE_ETH_RSS_NONFRAG_IPV4_UDP RTE_BIT64(5)
575 #define ETH_RSS_NONFRAG_IPV4_UDP RTE_ETH_RSS_NONFRAG_IPV4_UDP
576 #define RTE_ETH_RSS_NONFRAG_IPV4_SCTP RTE_BIT64(6)
577 #define ETH_RSS_NONFRAG_IPV4_SCTP RTE_ETH_RSS_NONFRAG_IPV4_SCTP
578 #define RTE_ETH_RSS_NONFRAG_IPV4_OTHER RTE_BIT64(7)
579 #define ETH_RSS_NONFRAG_IPV4_OTHER RTE_ETH_RSS_NONFRAG_IPV4_OTHER
580 #define RTE_ETH_RSS_IPV6 RTE_BIT64(8)
581 #define ETH_RSS_IPV6 RTE_ETH_RSS_IPV6
582 #define RTE_ETH_RSS_FRAG_IPV6 RTE_BIT64(9)
583 #define ETH_RSS_FRAG_IPV6 RTE_ETH_RSS_FRAG_IPV6
584 #define RTE_ETH_RSS_NONFRAG_IPV6_TCP RTE_BIT64(10)
585 #define ETH_RSS_NONFRAG_IPV6_TCP RTE_ETH_RSS_NONFRAG_IPV6_TCP
586 #define RTE_ETH_RSS_NONFRAG_IPV6_UDP RTE_BIT64(11)
587 #define ETH_RSS_NONFRAG_IPV6_UDP RTE_ETH_RSS_NONFRAG_IPV6_UDP
588 #define RTE_ETH_RSS_NONFRAG_IPV6_SCTP RTE_BIT64(12)
589 #define ETH_RSS_NONFRAG_IPV6_SCTP RTE_ETH_RSS_NONFRAG_IPV6_SCTP
590 #define RTE_ETH_RSS_NONFRAG_IPV6_OTHER RTE_BIT64(13)
591 #define ETH_RSS_NONFRAG_IPV6_OTHER RTE_ETH_RSS_NONFRAG_IPV6_OTHER
592 #define RTE_ETH_RSS_L2_PAYLOAD RTE_BIT64(14)
593 #define ETH_RSS_L2_PAYLOAD RTE_ETH_RSS_L2_PAYLOAD
594 #define RTE_ETH_RSS_IPV6_EX RTE_BIT64(15)
595 #define ETH_RSS_IPV6_EX RTE_ETH_RSS_IPV6_EX
596 #define RTE_ETH_RSS_IPV6_TCP_EX RTE_BIT64(16)
597 #define ETH_RSS_IPV6_TCP_EX RTE_ETH_RSS_IPV6_TCP_EX
598 #define RTE_ETH_RSS_IPV6_UDP_EX RTE_BIT64(17)
599 #define ETH_RSS_IPV6_UDP_EX RTE_ETH_RSS_IPV6_UDP_EX
600 #define RTE_ETH_RSS_PORT RTE_BIT64(18)
601 #define ETH_RSS_PORT RTE_ETH_RSS_PORT
602 #define RTE_ETH_RSS_VXLAN RTE_BIT64(19)
603 #define ETH_RSS_VXLAN RTE_ETH_RSS_VXLAN
604 #define RTE_ETH_RSS_GENEVE RTE_BIT64(20)
605 #define ETH_RSS_GENEVE RTE_ETH_RSS_GENEVE
606 #define RTE_ETH_RSS_NVGRE RTE_BIT64(21)
607 #define ETH_RSS_NVGRE RTE_ETH_RSS_NVGRE
608 #define RTE_ETH_RSS_GTPU RTE_BIT64(23)
609 #define ETH_RSS_GTPU RTE_ETH_RSS_GTPU
610 #define RTE_ETH_RSS_ETH RTE_BIT64(24)
611 #define ETH_RSS_ETH RTE_ETH_RSS_ETH
612 #define RTE_ETH_RSS_S_VLAN RTE_BIT64(25)
613 #define ETH_RSS_S_VLAN RTE_ETH_RSS_S_VLAN
614 #define RTE_ETH_RSS_C_VLAN RTE_BIT64(26)
615 #define ETH_RSS_C_VLAN RTE_ETH_RSS_C_VLAN
616 #define RTE_ETH_RSS_ESP RTE_BIT64(27)
617 #define ETH_RSS_ESP RTE_ETH_RSS_ESP
618 #define RTE_ETH_RSS_AH RTE_BIT64(28)
619 #define ETH_RSS_AH RTE_ETH_RSS_AH
620 #define RTE_ETH_RSS_L2TPV3 RTE_BIT64(29)
621 #define ETH_RSS_L2TPV3 RTE_ETH_RSS_L2TPV3
622 #define RTE_ETH_RSS_PFCP RTE_BIT64(30)
623 #define ETH_RSS_PFCP RTE_ETH_RSS_PFCP
624 #define RTE_ETH_RSS_PPPOE RTE_BIT64(31)
625 #define ETH_RSS_PPPOE RTE_ETH_RSS_PPPOE
626 #define RTE_ETH_RSS_ECPRI RTE_BIT64(32)
627 #define ETH_RSS_ECPRI RTE_ETH_RSS_ECPRI
628 #define RTE_ETH_RSS_MPLS RTE_BIT64(33)
629 #define ETH_RSS_MPLS RTE_ETH_RSS_MPLS
630 #define RTE_ETH_RSS_IPV4_CHKSUM RTE_BIT64(34)
631 #define ETH_RSS_IPV4_CHKSUM RTE_ETH_RSS_IPV4_CHKSUM
645 #define RTE_ETH_RSS_L4_CHKSUM RTE_BIT64(35)
646 #define ETH_RSS_L4_CHKSUM RTE_ETH_RSS_L4_CHKSUM
657 #define RTE_ETH_RSS_L3_SRC_ONLY RTE_BIT64(63)
658 #define ETH_RSS_L3_SRC_ONLY RTE_ETH_RSS_L3_SRC_ONLY
659 #define RTE_ETH_RSS_L3_DST_ONLY RTE_BIT64(62)
660 #define ETH_RSS_L3_DST_ONLY RTE_ETH_RSS_L3_DST_ONLY
661 #define RTE_ETH_RSS_L4_SRC_ONLY RTE_BIT64(61)
662 #define ETH_RSS_L4_SRC_ONLY RTE_ETH_RSS_L4_SRC_ONLY
663 #define RTE_ETH_RSS_L4_DST_ONLY RTE_BIT64(60)
664 #define ETH_RSS_L4_DST_ONLY RTE_ETH_RSS_L4_DST_ONLY
665 #define RTE_ETH_RSS_L2_SRC_ONLY RTE_BIT64(59)
666 #define ETH_RSS_L2_SRC_ONLY RTE_ETH_RSS_L2_SRC_ONLY
667 #define RTE_ETH_RSS_L2_DST_ONLY RTE_BIT64(58)
668 #define ETH_RSS_L2_DST_ONLY RTE_ETH_RSS_L2_DST_ONLY
676 #define RTE_ETH_RSS_L3_PRE32 RTE_BIT64(57)
677 #define RTE_ETH_RSS_L3_PRE40 RTE_BIT64(56)
678 #define RTE_ETH_RSS_L3_PRE48 RTE_BIT64(55)
679 #define RTE_ETH_RSS_L3_PRE56 RTE_BIT64(54)
680 #define RTE_ETH_RSS_L3_PRE64 RTE_BIT64(53)
681 #define RTE_ETH_RSS_L3_PRE96 RTE_BIT64(52)
696 #define RTE_ETH_RSS_LEVEL_PMD_DEFAULT (UINT64_C(0) << 50)
697 #define ETH_RSS_LEVEL_PMD_DEFAULT RTE_ETH_RSS_LEVEL_PMD_DEFAULT
703 #define RTE_ETH_RSS_LEVEL_OUTERMOST (UINT64_C(1) << 50)
704 #define ETH_RSS_LEVEL_OUTERMOST RTE_ETH_RSS_LEVEL_OUTERMOST
710 #define RTE_ETH_RSS_LEVEL_INNERMOST (UINT64_C(2) << 50)
711 #define ETH_RSS_LEVEL_INNERMOST RTE_ETH_RSS_LEVEL_INNERMOST
712 #define RTE_ETH_RSS_LEVEL_MASK (UINT64_C(3) << 50)
713 #define ETH_RSS_LEVEL_MASK RTE_ETH_RSS_LEVEL_MASK
715 #define RTE_ETH_RSS_LEVEL(rss_hf) ((rss_hf & RTE_ETH_RSS_LEVEL_MASK) >> 50)
716 #define ETH_RSS_LEVEL(rss_hf) RTE_ETH_RSS_LEVEL(rss_hf)
728 static inline uint64_t
731 if ((rss_hf & RTE_ETH_RSS_L3_SRC_ONLY) && (rss_hf & RTE_ETH_RSS_L3_DST_ONLY))
732 rss_hf &= ~(RTE_ETH_RSS_L3_SRC_ONLY | RTE_ETH_RSS_L3_DST_ONLY);
734 if ((rss_hf & RTE_ETH_RSS_L4_SRC_ONLY) && (rss_hf & RTE_ETH_RSS_L4_DST_ONLY))
735 rss_hf &= ~(RTE_ETH_RSS_L4_SRC_ONLY | RTE_ETH_RSS_L4_DST_ONLY);
740 #define RTE_ETH_RSS_IPV6_PRE32 ( \
742 RTE_ETH_RSS_L3_PRE32)
743 #define ETH_RSS_IPV6_PRE32 RTE_ETH_RSS_IPV6_PRE32
745 #define RTE_ETH_RSS_IPV6_PRE40 ( \
747 RTE_ETH_RSS_L3_PRE40)
748 #define ETH_RSS_IPV6_PRE40 RTE_ETH_RSS_IPV6_PRE40
750 #define RTE_ETH_RSS_IPV6_PRE48 ( \
752 RTE_ETH_RSS_L3_PRE48)
753 #define ETH_RSS_IPV6_PRE48 RTE_ETH_RSS_IPV6_PRE48
755 #define RTE_ETH_RSS_IPV6_PRE56 ( \
757 RTE_ETH_RSS_L3_PRE56)
758 #define ETH_RSS_IPV6_PRE56 RTE_ETH_RSS_IPV6_PRE56
760 #define RTE_ETH_RSS_IPV6_PRE64 ( \
762 RTE_ETH_RSS_L3_PRE64)
763 #define ETH_RSS_IPV6_PRE64 RTE_ETH_RSS_IPV6_PRE64
765 #define RTE_ETH_RSS_IPV6_PRE96 ( \
767 RTE_ETH_RSS_L3_PRE96)
768 #define ETH_RSS_IPV6_PRE96 RTE_ETH_RSS_IPV6_PRE96
770 #define RTE_ETH_RSS_IPV6_PRE32_UDP ( \
771 RTE_ETH_RSS_NONFRAG_IPV6_UDP | \
772 RTE_ETH_RSS_L3_PRE32)
773 #define ETH_RSS_IPV6_PRE32_UDP RTE_ETH_RSS_IPV6_PRE32_UDP
775 #define RTE_ETH_RSS_IPV6_PRE40_UDP ( \
776 RTE_ETH_RSS_NONFRAG_IPV6_UDP | \
777 RTE_ETH_RSS_L3_PRE40)
778 #define ETH_RSS_IPV6_PRE40_UDP RTE_ETH_RSS_IPV6_PRE40_UDP
780 #define RTE_ETH_RSS_IPV6_PRE48_UDP ( \
781 RTE_ETH_RSS_NONFRAG_IPV6_UDP | \
782 RTE_ETH_RSS_L3_PRE48)
783 #define ETH_RSS_IPV6_PRE48_UDP RTE_ETH_RSS_IPV6_PRE48_UDP
785 #define RTE_ETH_RSS_IPV6_PRE56_UDP ( \
786 RTE_ETH_RSS_NONFRAG_IPV6_UDP | \
787 RTE_ETH_RSS_L3_PRE56)
788 #define ETH_RSS_IPV6_PRE56_UDP RTE_ETH_RSS_IPV6_PRE56_UDP
790 #define RTE_ETH_RSS_IPV6_PRE64_UDP ( \
791 RTE_ETH_RSS_NONFRAG_IPV6_UDP | \
792 RTE_ETH_RSS_L3_PRE64)
793 #define ETH_RSS_IPV6_PRE64_UDP RTE_ETH_RSS_IPV6_PRE64_UDP
795 #define RTE_ETH_RSS_IPV6_PRE96_UDP ( \
796 RTE_ETH_RSS_NONFRAG_IPV6_UDP | \
797 RTE_ETH_RSS_L3_PRE96)
798 #define ETH_RSS_IPV6_PRE96_UDP RTE_ETH_RSS_IPV6_PRE96_UDP
800 #define RTE_ETH_RSS_IPV6_PRE32_TCP ( \
801 RTE_ETH_RSS_NONFRAG_IPV6_TCP | \
802 RTE_ETH_RSS_L3_PRE32)
803 #define ETH_RSS_IPV6_PRE32_TCP RTE_ETH_RSS_IPV6_PRE32_TCP
805 #define RTE_ETH_RSS_IPV6_PRE40_TCP ( \
806 RTE_ETH_RSS_NONFRAG_IPV6_TCP | \
807 RTE_ETH_RSS_L3_PRE40)
808 #define ETH_RSS_IPV6_PRE40_TCP RTE_ETH_RSS_IPV6_PRE40_TCP
810 #define RTE_ETH_RSS_IPV6_PRE48_TCP ( \
811 RTE_ETH_RSS_NONFRAG_IPV6_TCP | \
812 RTE_ETH_RSS_L3_PRE48)
813 #define ETH_RSS_IPV6_PRE48_TCP RTE_ETH_RSS_IPV6_PRE48_TCP
815 #define RTE_ETH_RSS_IPV6_PRE56_TCP ( \
816 RTE_ETH_RSS_NONFRAG_IPV6_TCP | \
817 RTE_ETH_RSS_L3_PRE56)
818 #define ETH_RSS_IPV6_PRE56_TCP RTE_ETH_RSS_IPV6_PRE56_TCP
820 #define RTE_ETH_RSS_IPV6_PRE64_TCP ( \
821 RTE_ETH_RSS_NONFRAG_IPV6_TCP | \
822 RTE_ETH_RSS_L3_PRE64)
823 #define ETH_RSS_IPV6_PRE64_TCP RTE_ETH_RSS_IPV6_PRE64_TCP
825 #define RTE_ETH_RSS_IPV6_PRE96_TCP ( \
826 RTE_ETH_RSS_NONFRAG_IPV6_TCP | \
827 RTE_ETH_RSS_L3_PRE96)
828 #define ETH_RSS_IPV6_PRE96_TCP RTE_ETH_RSS_IPV6_PRE96_TCP
830 #define RTE_ETH_RSS_IPV6_PRE32_SCTP ( \
831 RTE_ETH_RSS_NONFRAG_IPV6_SCTP | \
832 RTE_ETH_RSS_L3_PRE32)
833 #define ETH_RSS_IPV6_PRE32_SCTP RTE_ETH_RSS_IPV6_PRE32_SCTP
835 #define RTE_ETH_RSS_IPV6_PRE40_SCTP ( \
836 RTE_ETH_RSS_NONFRAG_IPV6_SCTP | \
837 RTE_ETH_RSS_L3_PRE40)
838 #define ETH_RSS_IPV6_PRE40_SCTP RTE_ETH_RSS_IPV6_PRE40_SCTP
840 #define RTE_ETH_RSS_IPV6_PRE48_SCTP ( \
841 RTE_ETH_RSS_NONFRAG_IPV6_SCTP | \
842 RTE_ETH_RSS_L3_PRE48)
843 #define ETH_RSS_IPV6_PRE48_SCTP RTE_ETH_RSS_IPV6_PRE48_SCTP
845 #define RTE_ETH_RSS_IPV6_PRE56_SCTP ( \
846 RTE_ETH_RSS_NONFRAG_IPV6_SCTP | \
847 RTE_ETH_RSS_L3_PRE56)
848 #define ETH_RSS_IPV6_PRE56_SCTP RTE_ETH_RSS_IPV6_PRE56_SCTP
850 #define RTE_ETH_RSS_IPV6_PRE64_SCTP ( \
851 RTE_ETH_RSS_NONFRAG_IPV6_SCTP | \
852 RTE_ETH_RSS_L3_PRE64)
853 #define ETH_RSS_IPV6_PRE64_SCTP RTE_ETH_RSS_IPV6_PRE64_SCTP
855 #define RTE_ETH_RSS_IPV6_PRE96_SCTP ( \
856 RTE_ETH_RSS_NONFRAG_IPV6_SCTP | \
857 RTE_ETH_RSS_L3_PRE96)
858 #define ETH_RSS_IPV6_PRE96_SCTP RTE_ETH_RSS_IPV6_PRE96_SCTP
860 #define RTE_ETH_RSS_IP ( \
862 RTE_ETH_RSS_FRAG_IPV4 | \
863 RTE_ETH_RSS_NONFRAG_IPV4_OTHER | \
865 RTE_ETH_RSS_FRAG_IPV6 | \
866 RTE_ETH_RSS_NONFRAG_IPV6_OTHER | \
868 #define ETH_RSS_IP RTE_ETH_RSS_IP
870 #define RTE_ETH_RSS_UDP ( \
871 RTE_ETH_RSS_NONFRAG_IPV4_UDP | \
872 RTE_ETH_RSS_NONFRAG_IPV6_UDP | \
873 RTE_ETH_RSS_IPV6_UDP_EX)
874 #define ETH_RSS_UDP RTE_ETH_RSS_UDP
876 #define RTE_ETH_RSS_TCP ( \
877 RTE_ETH_RSS_NONFRAG_IPV4_TCP | \
878 RTE_ETH_RSS_NONFRAG_IPV6_TCP | \
879 RTE_ETH_RSS_IPV6_TCP_EX)
880 #define ETH_RSS_TCP RTE_ETH_RSS_TCP
882 #define RTE_ETH_RSS_SCTP ( \
883 RTE_ETH_RSS_NONFRAG_IPV4_SCTP | \
884 RTE_ETH_RSS_NONFRAG_IPV6_SCTP)
885 #define ETH_RSS_SCTP RTE_ETH_RSS_SCTP
887 #define RTE_ETH_RSS_TUNNEL ( \
888 RTE_ETH_RSS_VXLAN | \
889 RTE_ETH_RSS_GENEVE | \
891 #define ETH_RSS_TUNNEL RTE_ETH_RSS_TUNNEL
893 #define RTE_ETH_RSS_VLAN ( \
894 RTE_ETH_RSS_S_VLAN | \
896 #define ETH_RSS_VLAN RTE_ETH_RSS_VLAN
899 #define RTE_ETH_RSS_PROTO_MASK ( \
901 RTE_ETH_RSS_FRAG_IPV4 | \
902 RTE_ETH_RSS_NONFRAG_IPV4_TCP | \
903 RTE_ETH_RSS_NONFRAG_IPV4_UDP | \
904 RTE_ETH_RSS_NONFRAG_IPV4_SCTP | \
905 RTE_ETH_RSS_NONFRAG_IPV4_OTHER | \
907 RTE_ETH_RSS_FRAG_IPV6 | \
908 RTE_ETH_RSS_NONFRAG_IPV6_TCP | \
909 RTE_ETH_RSS_NONFRAG_IPV6_UDP | \
910 RTE_ETH_RSS_NONFRAG_IPV6_SCTP | \
911 RTE_ETH_RSS_NONFRAG_IPV6_OTHER | \
912 RTE_ETH_RSS_L2_PAYLOAD | \
913 RTE_ETH_RSS_IPV6_EX | \
914 RTE_ETH_RSS_IPV6_TCP_EX | \
915 RTE_ETH_RSS_IPV6_UDP_EX | \
917 RTE_ETH_RSS_VXLAN | \
918 RTE_ETH_RSS_GENEVE | \
919 RTE_ETH_RSS_NVGRE | \
921 #define ETH_RSS_PROTO_MASK RTE_ETH_RSS_PROTO_MASK
928 #define RTE_ETH_RSS_RETA_SIZE_64 64
929 #define ETH_RSS_RETA_SIZE_64 RTE_ETH_RSS_RETA_SIZE_64
930 #define RTE_ETH_RSS_RETA_SIZE_128 128
931 #define ETH_RSS_RETA_SIZE_128 RTE_ETH_RSS_RETA_SIZE_128
932 #define RTE_ETH_RSS_RETA_SIZE_256 256
933 #define ETH_RSS_RETA_SIZE_256 RTE_ETH_RSS_RETA_SIZE_256
934 #define RTE_ETH_RSS_RETA_SIZE_512 512
935 #define ETH_RSS_RETA_SIZE_512 RTE_ETH_RSS_RETA_SIZE_512
936 #define RTE_ETH_RETA_GROUP_SIZE 64
937 #define RTE_RETA_GROUP_SIZE RTE_ETH_RETA_GROUP_SIZE
940 #define RTE_ETH_VMDQ_MAX_VLAN_FILTERS 64
941 #define ETH_VMDQ_MAX_VLAN_FILTERS RTE_ETH_VMDQ_MAX_VLAN_FILTERS
942 #define RTE_ETH_DCB_NUM_USER_PRIORITIES 8
943 #define ETH_DCB_NUM_USER_PRIORITIES RTE_ETH_DCB_NUM_USER_PRIORITIES
944 #define RTE_ETH_VMDQ_DCB_NUM_QUEUES 128
945 #define ETH_VMDQ_DCB_NUM_QUEUES RTE_ETH_VMDQ_DCB_NUM_QUEUES
946 #define RTE_ETH_DCB_NUM_QUEUES 128
947 #define ETH_DCB_NUM_QUEUES RTE_ETH_DCB_NUM_QUEUES
951 #define RTE_ETH_DCB_PG_SUPPORT RTE_BIT32(0)
952 #define ETH_DCB_PG_SUPPORT RTE_ETH_DCB_PG_SUPPORT
953 #define RTE_ETH_DCB_PFC_SUPPORT RTE_BIT32(1)
954 #define ETH_DCB_PFC_SUPPORT RTE_ETH_DCB_PFC_SUPPORT
958 #define RTE_ETH_VLAN_STRIP_OFFLOAD 0x0001
959 #define ETH_VLAN_STRIP_OFFLOAD RTE_ETH_VLAN_STRIP_OFFLOAD
960 #define RTE_ETH_VLAN_FILTER_OFFLOAD 0x0002
961 #define ETH_VLAN_FILTER_OFFLOAD RTE_ETH_VLAN_FILTER_OFFLOAD
962 #define RTE_ETH_VLAN_EXTEND_OFFLOAD 0x0004
963 #define ETH_VLAN_EXTEND_OFFLOAD RTE_ETH_VLAN_EXTEND_OFFLOAD
964 #define RTE_ETH_QINQ_STRIP_OFFLOAD 0x0008
965 #define ETH_QINQ_STRIP_OFFLOAD RTE_ETH_QINQ_STRIP_OFFLOAD
967 #define RTE_ETH_VLAN_STRIP_MASK 0x0001
968 #define ETH_VLAN_STRIP_MASK RTE_ETH_VLAN_STRIP_MASK
969 #define RTE_ETH_VLAN_FILTER_MASK 0x0002
970 #define ETH_VLAN_FILTER_MASK RTE_ETH_VLAN_FILTER_MASK
971 #define RTE_ETH_VLAN_EXTEND_MASK 0x0004
972 #define ETH_VLAN_EXTEND_MASK RTE_ETH_VLAN_EXTEND_MASK
973 #define RTE_ETH_QINQ_STRIP_MASK 0x0008
974 #define ETH_QINQ_STRIP_MASK RTE_ETH_QINQ_STRIP_MASK
975 #define RTE_ETH_VLAN_ID_MAX 0x0FFF
976 #define ETH_VLAN_ID_MAX RTE_ETH_VLAN_ID_MAX
980 #define RTE_ETH_NUM_RECEIVE_MAC_ADDR 128
981 #define ETH_NUM_RECEIVE_MAC_ADDR RTE_ETH_NUM_RECEIVE_MAC_ADDR
984 #define RTE_ETH_VMDQ_NUM_UC_HASH_ARRAY 128
985 #define ETH_VMDQ_NUM_UC_HASH_ARRAY RTE_ETH_VMDQ_NUM_UC_HASH_ARRAY
991 #define RTE_ETH_VMDQ_ACCEPT_UNTAG RTE_BIT32(0)
992 #define ETH_VMDQ_ACCEPT_UNTAG RTE_ETH_VMDQ_ACCEPT_UNTAG
994 #define RTE_ETH_VMDQ_ACCEPT_HASH_MC RTE_BIT32(1)
995 #define ETH_VMDQ_ACCEPT_HASH_MC RTE_ETH_VMDQ_ACCEPT_HASH_MC
997 #define RTE_ETH_VMDQ_ACCEPT_HASH_UC RTE_BIT32(2)
998 #define ETH_VMDQ_ACCEPT_HASH_UC RTE_ETH_VMDQ_ACCEPT_HASH_UC
1000 #define RTE_ETH_VMDQ_ACCEPT_BROADCAST RTE_BIT32(3)
1001 #define ETH_VMDQ_ACCEPT_BROADCAST RTE_ETH_VMDQ_ACCEPT_BROADCAST
1003 #define RTE_ETH_VMDQ_ACCEPT_MULTICAST RTE_BIT32(4)
1004 #define ETH_VMDQ_ACCEPT_MULTICAST RTE_ETH_VMDQ_ACCEPT_MULTICAST
1017 uint16_t
reta[RTE_ETH_RETA_GROUP_SIZE];
1028 #define ETH_4_TCS RTE_ETH_4_TCS
1029 #define ETH_8_TCS RTE_ETH_8_TCS
1041 #define ETH_8_POOLS RTE_ETH_8_POOLS
1042 #define ETH_16_POOLS RTE_ETH_16_POOLS
1043 #define ETH_32_POOLS RTE_ETH_32_POOLS
1044 #define ETH_64_POOLS RTE_ETH_64_POOLS
1047 struct rte_eth_dcb_rx_conf {
1053 struct rte_eth_vmdq_dcb_tx_conf {
1059 struct rte_eth_dcb_tx_conf {
1065 struct rte_eth_vmdq_tx_conf {
1277 #define RTE_ETH_MAX_HAIRPIN_PEERS 32
1368 #define RTE_FC_NONE RTE_ETH_FC_NONE
1369 #define RTE_FC_RX_PAUSE RTE_ETH_FC_RX_PAUSE
1370 #define RTE_FC_TX_PAUSE RTE_ETH_FC_TX_PAUSE
1371 #define RTE_FC_FULL RTE_ETH_FC_FULL
1403 RTE_ETH_TUNNEL_TYPE_NONE = 0,
1404 RTE_ETH_TUNNEL_TYPE_VXLAN,
1405 RTE_ETH_TUNNEL_TYPE_GENEVE,
1406 RTE_ETH_TUNNEL_TYPE_TEREDO,
1407 RTE_ETH_TUNNEL_TYPE_NVGRE,
1408 RTE_ETH_TUNNEL_TYPE_IP_IN_GRE,
1409 RTE_ETH_L2_TUNNEL_TYPE_E_TAG,
1410 RTE_ETH_TUNNEL_TYPE_VXLAN_GPE,
1411 RTE_ETH_TUNNEL_TYPE_ECPRI,
1412 RTE_ETH_TUNNEL_TYPE_MAX,
1415 #define RTE_TUNNEL_TYPE_NONE RTE_ETH_TUNNEL_TYPE_NONE
1416 #define RTE_TUNNEL_TYPE_VXLAN RTE_ETH_TUNNEL_TYPE_VXLAN
1417 #define RTE_TUNNEL_TYPE_GENEVE RTE_ETH_TUNNEL_TYPE_GENEVE
1418 #define RTE_TUNNEL_TYPE_TEREDO RTE_ETH_TUNNEL_TYPE_TEREDO
1419 #define RTE_TUNNEL_TYPE_NVGRE RTE_ETH_TUNNEL_TYPE_NVGRE
1420 #define RTE_TUNNEL_TYPE_IP_IN_GRE RTE_ETH_TUNNEL_TYPE_IP_IN_GRE
1421 #define RTE_L2_TUNNEL_TYPE_E_TAG RTE_ETH_L2_TUNNEL_TYPE_E_TAG
1422 #define RTE_TUNNEL_TYPE_VXLAN_GPE RTE_ETH_TUNNEL_TYPE_VXLAN_GPE
1423 #define RTE_TUNNEL_TYPE_ECPRI RTE_ETH_TUNNEL_TYPE_ECPRI
1424 #define RTE_TUNNEL_TYPE_MAX RTE_ETH_TUNNEL_TYPE_MAX
1438 #define rte_fdir_pballoc_type rte_eth_fdir_pballoc_type
1440 #define RTE_FDIR_PBALLOC_64K RTE_ETH_FDIR_PBALLOC_64K
1441 #define RTE_FDIR_PBALLOC_128K RTE_ETH_FDIR_PBALLOC_128K
1442 #define RTE_FDIR_PBALLOC_256K RTE_ETH_FDIR_PBALLOC_256K
1470 #define rte_fdir_conf rte_eth_fdir_conf
1498 #define rte_intr_conf rte_eth_intr_conf
1547 #define RTE_ETH_RX_OFFLOAD_VLAN_STRIP RTE_BIT64(0)
1548 #define DEV_RX_OFFLOAD_VLAN_STRIP RTE_ETH_RX_OFFLOAD_VLAN_STRIP
1549 #define RTE_ETH_RX_OFFLOAD_IPV4_CKSUM RTE_BIT64(1)
1550 #define DEV_RX_OFFLOAD_IPV4_CKSUM RTE_ETH_RX_OFFLOAD_IPV4_CKSUM
1551 #define RTE_ETH_RX_OFFLOAD_UDP_CKSUM RTE_BIT64(2)
1552 #define DEV_RX_OFFLOAD_UDP_CKSUM RTE_ETH_RX_OFFLOAD_UDP_CKSUM
1553 #define RTE_ETH_RX_OFFLOAD_TCP_CKSUM RTE_BIT64(3)
1554 #define DEV_RX_OFFLOAD_TCP_CKSUM RTE_ETH_RX_OFFLOAD_TCP_CKSUM
1555 #define RTE_ETH_RX_OFFLOAD_TCP_LRO RTE_BIT64(4)
1556 #define DEV_RX_OFFLOAD_TCP_LRO RTE_ETH_RX_OFFLOAD_TCP_LRO
1557 #define RTE_ETH_RX_OFFLOAD_QINQ_STRIP RTE_BIT64(5)
1558 #define DEV_RX_OFFLOAD_QINQ_STRIP RTE_ETH_RX_OFFLOAD_QINQ_STRIP
1559 #define RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM RTE_BIT64(6)
1560 #define DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM
1561 #define RTE_ETH_RX_OFFLOAD_MACSEC_STRIP RTE_BIT64(7)
1562 #define DEV_RX_OFFLOAD_MACSEC_STRIP RTE_ETH_RX_OFFLOAD_MACSEC_STRIP
1563 #define RTE_ETH_RX_OFFLOAD_HEADER_SPLIT RTE_BIT64(8)
1564 #define DEV_RX_OFFLOAD_HEADER_SPLIT RTE_ETH_RX_OFFLOAD_HEADER_SPLIT
1565 #define RTE_ETH_RX_OFFLOAD_VLAN_FILTER RTE_BIT64(9)
1566 #define DEV_RX_OFFLOAD_VLAN_FILTER RTE_ETH_RX_OFFLOAD_VLAN_FILTER
1567 #define RTE_ETH_RX_OFFLOAD_VLAN_EXTEND RTE_BIT64(10)
1568 #define DEV_RX_OFFLOAD_VLAN_EXTEND RTE_ETH_RX_OFFLOAD_VLAN_EXTEND
1569 #define RTE_ETH_RX_OFFLOAD_SCATTER RTE_BIT64(13)
1570 #define DEV_RX_OFFLOAD_SCATTER RTE_ETH_RX_OFFLOAD_SCATTER
1576 #define RTE_ETH_RX_OFFLOAD_TIMESTAMP RTE_BIT64(14)
1577 #define DEV_RX_OFFLOAD_TIMESTAMP RTE_ETH_RX_OFFLOAD_TIMESTAMP
1578 #define RTE_ETH_RX_OFFLOAD_SECURITY RTE_BIT64(15)
1579 #define DEV_RX_OFFLOAD_SECURITY RTE_ETH_RX_OFFLOAD_SECURITY
1580 #define RTE_ETH_RX_OFFLOAD_KEEP_CRC RTE_BIT64(16)
1581 #define DEV_RX_OFFLOAD_KEEP_CRC RTE_ETH_RX_OFFLOAD_KEEP_CRC
1582 #define RTE_ETH_RX_OFFLOAD_SCTP_CKSUM RTE_BIT64(17)
1583 #define DEV_RX_OFFLOAD_SCTP_CKSUM RTE_ETH_RX_OFFLOAD_SCTP_CKSUM
1584 #define RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM RTE_BIT64(18)
1585 #define DEV_RX_OFFLOAD_OUTER_UDP_CKSUM RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM
1586 #define RTE_ETH_RX_OFFLOAD_RSS_HASH RTE_BIT64(19)
1587 #define DEV_RX_OFFLOAD_RSS_HASH RTE_ETH_RX_OFFLOAD_RSS_HASH
1588 #define RTE_ETH_RX_OFFLOAD_BUFFER_SPLIT RTE_BIT64(20)
1590 #define RTE_ETH_RX_OFFLOAD_CHECKSUM (RTE_ETH_RX_OFFLOAD_IPV4_CKSUM | \
1591 RTE_ETH_RX_OFFLOAD_UDP_CKSUM | \
1592 RTE_ETH_RX_OFFLOAD_TCP_CKSUM)
1593 #define DEV_RX_OFFLOAD_CHECKSUM RTE_ETH_RX_OFFLOAD_CHECKSUM
1594 #define RTE_ETH_RX_OFFLOAD_VLAN (RTE_ETH_RX_OFFLOAD_VLAN_STRIP | \
1595 RTE_ETH_RX_OFFLOAD_VLAN_FILTER | \
1596 RTE_ETH_RX_OFFLOAD_VLAN_EXTEND | \
1597 RTE_ETH_RX_OFFLOAD_QINQ_STRIP)
1598 #define DEV_RX_OFFLOAD_VLAN RTE_ETH_RX_OFFLOAD_VLAN
1608 #define RTE_ETH_TX_OFFLOAD_VLAN_INSERT RTE_BIT64(0)
1609 #define DEV_TX_OFFLOAD_VLAN_INSERT RTE_ETH_TX_OFFLOAD_VLAN_INSERT
1610 #define RTE_ETH_TX_OFFLOAD_IPV4_CKSUM RTE_BIT64(1)
1611 #define DEV_TX_OFFLOAD_IPV4_CKSUM RTE_ETH_TX_OFFLOAD_IPV4_CKSUM
1612 #define RTE_ETH_TX_OFFLOAD_UDP_CKSUM RTE_BIT64(2)
1613 #define DEV_TX_OFFLOAD_UDP_CKSUM RTE_ETH_TX_OFFLOAD_UDP_CKSUM
1614 #define RTE_ETH_TX_OFFLOAD_TCP_CKSUM RTE_BIT64(3)
1615 #define DEV_TX_OFFLOAD_TCP_CKSUM RTE_ETH_TX_OFFLOAD_TCP_CKSUM
1616 #define RTE_ETH_TX_OFFLOAD_SCTP_CKSUM RTE_BIT64(4)
1617 #define DEV_TX_OFFLOAD_SCTP_CKSUM RTE_ETH_TX_OFFLOAD_SCTP_CKSUM
1618 #define RTE_ETH_TX_OFFLOAD_TCP_TSO RTE_BIT64(5)
1619 #define DEV_TX_OFFLOAD_TCP_TSO RTE_ETH_TX_OFFLOAD_TCP_TSO
1620 #define RTE_ETH_TX_OFFLOAD_UDP_TSO RTE_BIT64(6)
1621 #define DEV_TX_OFFLOAD_UDP_TSO RTE_ETH_TX_OFFLOAD_UDP_TSO
1622 #define RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM RTE_BIT64(7)
1623 #define DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM
1624 #define RTE_ETH_TX_OFFLOAD_QINQ_INSERT RTE_BIT64(8)
1625 #define DEV_TX_OFFLOAD_QINQ_INSERT RTE_ETH_TX_OFFLOAD_QINQ_INSERT
1626 #define RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO RTE_BIT64(9)
1627 #define DEV_TX_OFFLOAD_VXLAN_TNL_TSO RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO
1628 #define RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO RTE_BIT64(10)
1629 #define DEV_TX_OFFLOAD_GRE_TNL_TSO RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO
1630 #define RTE_ETH_TX_OFFLOAD_IPIP_TNL_TSO RTE_BIT64(11)
1631 #define DEV_TX_OFFLOAD_IPIP_TNL_TSO RTE_ETH_TX_OFFLOAD_IPIP_TNL_TSO
1632 #define RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO RTE_BIT64(12)
1633 #define DEV_TX_OFFLOAD_GENEVE_TNL_TSO RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO
1634 #define RTE_ETH_TX_OFFLOAD_MACSEC_INSERT RTE_BIT64(13)
1635 #define DEV_TX_OFFLOAD_MACSEC_INSERT RTE_ETH_TX_OFFLOAD_MACSEC_INSERT
1640 #define RTE_ETH_TX_OFFLOAD_MT_LOCKFREE RTE_BIT64(14)
1641 #define DEV_TX_OFFLOAD_MT_LOCKFREE RTE_ETH_TX_OFFLOAD_MT_LOCKFREE
1643 #define RTE_ETH_TX_OFFLOAD_MULTI_SEGS RTE_BIT64(15)
1644 #define DEV_TX_OFFLOAD_MULTI_SEGS RTE_ETH_TX_OFFLOAD_MULTI_SEGS
1650 #define RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE RTE_BIT64(16)
1651 #define DEV_TX_OFFLOAD_MBUF_FAST_FREE RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE
1652 #define RTE_ETH_TX_OFFLOAD_SECURITY RTE_BIT64(17)
1653 #define DEV_TX_OFFLOAD_SECURITY RTE_ETH_TX_OFFLOAD_SECURITY
1659 #define RTE_ETH_TX_OFFLOAD_UDP_TNL_TSO RTE_BIT64(18)
1660 #define DEV_TX_OFFLOAD_UDP_TNL_TSO RTE_ETH_TX_OFFLOAD_UDP_TNL_TSO
1666 #define RTE_ETH_TX_OFFLOAD_IP_TNL_TSO RTE_BIT64(19)
1667 #define DEV_TX_OFFLOAD_IP_TNL_TSO RTE_ETH_TX_OFFLOAD_IP_TNL_TSO
1669 #define RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM RTE_BIT64(20)
1670 #define DEV_TX_OFFLOAD_OUTER_UDP_CKSUM RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM
1676 #define RTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP RTE_BIT64(21)
1677 #define DEV_TX_OFFLOAD_SEND_ON_TIMESTAMP RTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP
1687 #define RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP RTE_BIT64(0)
1689 #define RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP RTE_BIT64(1)
1699 #define RTE_ETH_DEV_CAPA_RXQ_SHARE RTE_BIT64(2)
1701 #define RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP RTE_BIT64(3)
1703 #define RTE_ETH_DEV_CAPA_FLOW_SHARED_OBJECT_KEEP RTE_BIT64(4)
1711 #define RTE_ETH_DEV_FALLBACK_RX_RINGSIZE 512
1712 #define RTE_ETH_DEV_FALLBACK_TX_RINGSIZE 512
1713 #define RTE_ETH_DEV_FALLBACK_RX_NBQUEUES 1
1714 #define RTE_ETH_DEV_FALLBACK_TX_NBQUEUES 1
1731 #define RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID (UINT16_MAX)
1850 #define RTE_ETH_QUEUE_STATE_STOPPED 0
1851 #define RTE_ETH_QUEUE_STATE_STARTED 1
1852 #define RTE_ETH_QUEUE_STATE_HAIRPIN 2
1859 struct rte_eth_rxq_info {
1885 #define RTE_ETH_BURST_FLAG_PER_QUEUE RTE_BIT64(0)
1894 #define RTE_ETH_BURST_MODE_INFO_SIZE 1024
1895 char info[RTE_ETH_BURST_MODE_INFO_SIZE];
1899 #define RTE_ETH_XSTATS_NAME_SIZE 64
1933 #define RTE_ETH_DCB_NUM_TCS 8
1934 #define ETH_DCB_NUM_TCS RTE_ETH_DCB_NUM_TCS
1935 #define RTE_ETH_MAX_VMDQ_POOL 64
1936 #define ETH_MAX_VMDQ_POOL RTE_ETH_MAX_VMDQ_POOL
1947 } tc_rxq[RTE_ETH_MAX_VMDQ_POOL][RTE_ETH_DCB_NUM_TCS];
1952 } tc_txq[RTE_ETH_MAX_VMDQ_POOL][RTE_ETH_DCB_NUM_TCS];
1962 uint8_t tc_bws[RTE_ETH_DCB_NUM_TCS];
1979 #define RTE_ETH_FEC_MODE_TO_CAPA(x) RTE_BIT32(x)
1982 #define RTE_ETH_FEC_MODE_CAPA_MASK(x) RTE_BIT32(RTE_ETH_FEC_ ## x)
1985 struct rte_eth_fec_capa {
1990 #define RTE_ETH_ALL RTE_MAX_ETHPORTS
1993 #define RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, retval) do { \
1994 if (!rte_eth_dev_is_valid_port(port_id)) { \
1995 RTE_ETHDEV_LOG(ERR, "Invalid port_id=%u\n", port_id); \
2000 #define RTE_ETH_VALID_PORTID_OR_RET(port_id) do { \
2001 if (!rte_eth_dev_is_valid_port(port_id)) { \
2002 RTE_ETHDEV_LOG(ERR, "Invalid port_id=%u\n", port_id); \
2030 struct rte_mbuf *pkts[], uint16_t nb_pkts, uint16_t max_pkts,
2054 struct rte_mbuf *pkts[], uint16_t nb_pkts,
void *user_param);
2068 struct rte_eth_dev_sriov {
2070 uint8_t nb_q_per_pool;
2071 uint16_t def_vmdq_idx;
2072 uint16_t def_pool_q_idx;
2074 #define RTE_ETH_DEV_SRIOV(dev) ((dev)->data->sriov)
2076 #define RTE_ETH_NAME_MAX_LEN RTE_DEV_NAME_MAX_LEN
2078 #define RTE_ETH_DEV_NO_OWNER 0
2080 #define RTE_ETH_MAX_OWNER_NAME_LEN 64
2082 struct rte_eth_dev_owner {
2084 char name[RTE_ETH_MAX_OWNER_NAME_LEN];
2092 #define RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE RTE_BIT32(0)
2094 #define RTE_ETH_DEV_INTR_LSC RTE_BIT32(1)
2096 #define RTE_ETH_DEV_BONDED_SLAVE RTE_BIT32(2)
2098 #define RTE_ETH_DEV_INTR_RMV RTE_BIT32(3)
2100 #define RTE_ETH_DEV_REPRESENTOR RTE_BIT32(4)
2102 #define RTE_ETH_DEV_NOLIVE_MAC_ADDR RTE_BIT32(5)
2107 #define RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS RTE_BIT32(6)
2122 const uint64_t owner_id);
2127 #define RTE_ETH_FOREACH_DEV_OWNED_BY(p, o) \
2128 for (p = rte_eth_find_next_owned_by(0, o); \
2129 (unsigned int)p < (unsigned int)RTE_MAX_ETHPORTS; \
2130 p = rte_eth_find_next_owned_by(p + 1, o))
2145 #define RTE_ETH_FOREACH_DEV(p) \
2146 RTE_ETH_FOREACH_DEV_OWNED_BY(p, RTE_ETH_DEV_NO_OWNER)
2171 #define RTE_ETH_FOREACH_DEV_OF(port_id, parent) \
2172 for (port_id = rte_eth_find_next_of(0, parent); \
2173 port_id < RTE_MAX_ETHPORTS; \
2174 port_id = rte_eth_find_next_of(port_id + 1, parent))
2200 #define RTE_ETH_FOREACH_DEV_SIBLING(port_id, ref_port_id) \
2201 for (port_id = rte_eth_find_next_sibling(0, ref_port_id); \
2202 port_id < RTE_MAX_ETHPORTS; \
2203 port_id = rte_eth_find_next_sibling(port_id + 1, ref_port_id))
2236 const struct rte_eth_dev_owner *owner);
2253 const uint64_t owner_id);
2284 struct rte_eth_dev_owner *owner);
2395 uint16_t nb_tx_queue,
const struct rte_eth_conf *eth_conf);
2471 uint16_t nb_rx_desc,
unsigned int socket_id,
2504 (uint16_t port_id, uint16_t rx_queue_id, uint16_t nb_rx_desc,
2556 uint16_t nb_tx_desc,
unsigned int socket_id,
2586 (uint16_t port_id, uint16_t tx_queue_id, uint16_t nb_tx_desc,
2617 size_t len, uint32_t direction);
3177 uint64_t *values,
unsigned int size);
3234 uint16_t tx_queue_id, uint8_t stat_idx);
3255 uint16_t rx_queue_id,
3381 char *fw_version,
size_t fw_size);
3423 uint32_t *ptypes,
int num);
3455 uint32_t *set_ptypes,
unsigned int num);
3602 typedef void (*buffer_tx_error_fn)(
struct rte_mbuf **unsent, uint16_t count,
3610 buffer_tx_error_fn error_callback;
3611 void *error_userdata;
3624 #define RTE_ETH_TX_BUFFER_SIZE(sz) \
3625 (sizeof(struct rte_eth_dev_tx_buffer) + (sz) * sizeof(struct rte_mbuf *))
3666 buffer_tx_error_fn callback,
void *userdata);
3943 int epfd,
int op,
void *data);
4022 struct rte_eth_fec_capa *speed_fec_capa,
4199 uint16_t reta_size);
4221 uint16_t reta_size);
4388 struct rte_eth_rxtx_callback;
4415 const struct rte_eth_rxtx_callback *
4445 const struct rte_eth_rxtx_callback *
4474 const struct rte_eth_rxtx_callback *
4512 const struct rte_eth_rxtx_callback *user_cb);
4548 const struct rte_eth_rxtx_callback *user_cb);
4658 struct rte_power_monitor_cond *pmc);
4775 struct rte_dev_eeprom_info *
info);
4798 uint32_t nb_mc_addr);
4847 struct timespec *timestamp, uint32_t flags);
4865 struct timespec *timestamp);
5025 uint16_t *nb_rx_desc,
5026 uint16_t *nb_tx_desc);
5093 char name[RTE_DEV_NAME_MAX_LEN];
5138 #define RTE_ETH_RX_METADATA_USER_FLAG RTE_BIT64(0)
5141 #define RTE_ETH_RX_METADATA_USER_MARK RTE_BIT64(1)
5144 #define RTE_ETH_RX_METADATA_TUNNEL_ID RTE_BIT64(2)
5216 uint16_t rte_eth_call_rx_callbacks(uint16_t port_id, uint16_t queue_id,
5217 struct rte_mbuf **rx_pkts, uint16_t nb_rx, uint16_t nb_pkts,
5307 static inline uint16_t
5309 struct rte_mbuf **rx_pkts,
const uint16_t nb_pkts)
5312 struct rte_eth_fp_ops *p;
5315 #ifdef RTE_ETHDEV_DEBUG_RX
5316 if (port_id >= RTE_MAX_ETHPORTS ||
5317 queue_id >= RTE_MAX_QUEUES_PER_PORT) {
5319 "Invalid port_id=%u or queue_id=%u\n",
5326 p = &rte_eth_fp_ops[port_id];
5327 qd = p->rxq.data[queue_id];
5329 #ifdef RTE_ETHDEV_DEBUG_RX
5330 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, 0);
5333 RTE_ETHDEV_LOG(ERR,
"Invalid Rx queue_id=%u for port_id=%u\n",
5339 nb_rx = p->rx_pkt_burst(qd, rx_pkts, nb_pkts);
5341 #ifdef RTE_ETHDEV_RXTX_CALLBACKS
5351 cb = __atomic_load_n((
void **)&p->rxq.clbk[queue_id],
5354 nb_rx = rte_eth_call_rx_callbacks(port_id, queue_id,
5355 rx_pkts, nb_rx, nb_pkts, cb);
5359 rte_ethdev_trace_rx_burst(port_id, queue_id, (
void **)rx_pkts, nb_rx);
5379 struct rte_eth_fp_ops *p;
5382 if (port_id >= RTE_MAX_ETHPORTS ||
5383 queue_id >= RTE_MAX_QUEUES_PER_PORT) {
5385 "Invalid port_id=%u or queue_id=%u\n",
5391 p = &rte_eth_fp_ops[port_id];
5392 qd = p->rxq.data[queue_id];
5394 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5395 RTE_FUNC_PTR_OR_ERR_RET(*p->rx_queue_count, -ENOTSUP);
5399 return (
int)(*p->rx_queue_count)(qd);
5405 #define RTE_ETH_RX_DESC_AVAIL 0
5406 #define RTE_ETH_RX_DESC_DONE 1
5407 #define RTE_ETH_RX_DESC_UNAVAIL 2
5447 struct rte_eth_fp_ops *p;
5450 #ifdef RTE_ETHDEV_DEBUG_RX
5451 if (port_id >= RTE_MAX_ETHPORTS ||
5452 queue_id >= RTE_MAX_QUEUES_PER_PORT) {
5454 "Invalid port_id=%u or queue_id=%u\n",
5461 p = &rte_eth_fp_ops[port_id];
5462 qd = p->rxq.data[queue_id];
5464 #ifdef RTE_ETHDEV_DEBUG_RX
5465 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5469 RTE_FUNC_PTR_OR_ERR_RET(*p->rx_descriptor_status, -ENOTSUP);
5470 return (*p->rx_descriptor_status)(qd, offset);
5476 #define RTE_ETH_TX_DESC_FULL 0
5477 #define RTE_ETH_TX_DESC_DONE 1
5478 #define RTE_ETH_TX_DESC_UNAVAIL 2
5514 static inline int rte_eth_tx_descriptor_status(uint16_t port_id,
5515 uint16_t queue_id, uint16_t offset)
5517 struct rte_eth_fp_ops *p;
5520 #ifdef RTE_ETHDEV_DEBUG_TX
5521 if (port_id >= RTE_MAX_ETHPORTS ||
5522 queue_id >= RTE_MAX_QUEUES_PER_PORT) {
5524 "Invalid port_id=%u or queue_id=%u\n",
5531 p = &rte_eth_fp_ops[port_id];
5532 qd = p->txq.data[queue_id];
5534 #ifdef RTE_ETHDEV_DEBUG_TX
5535 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
5539 RTE_FUNC_PTR_OR_ERR_RET(*p->tx_descriptor_status, -ENOTSUP);
5540 return (*p->tx_descriptor_status)(qd, offset);
5562 uint16_t rte_eth_call_tx_callbacks(uint16_t port_id, uint16_t queue_id,
5563 struct rte_mbuf **tx_pkts, uint16_t nb_pkts,
void *opaque);
5631 static inline uint16_t
5633 struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
5635 struct rte_eth_fp_ops *p;
5638 #ifdef RTE_ETHDEV_DEBUG_TX
5639 if (port_id >= RTE_MAX_ETHPORTS ||
5640 queue_id >= RTE_MAX_QUEUES_PER_PORT) {
5642 "Invalid port_id=%u or queue_id=%u\n",
5649 p = &rte_eth_fp_ops[port_id];
5650 qd = p->txq.data[queue_id];
5652 #ifdef RTE_ETHDEV_DEBUG_TX
5653 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, 0);
5656 RTE_ETHDEV_LOG(ERR,
"Invalid Tx queue_id=%u for port_id=%u\n",
5662 #ifdef RTE_ETHDEV_RXTX_CALLBACKS
5672 cb = __atomic_load_n((
void **)&p->txq.clbk[queue_id],
5675 nb_pkts = rte_eth_call_tx_callbacks(port_id, queue_id,
5676 tx_pkts, nb_pkts, cb);
5680 nb_pkts = p->tx_pkt_burst(qd, tx_pkts, nb_pkts);
5682 rte_ethdev_trace_tx_burst(port_id, queue_id, (
void **)tx_pkts, nb_pkts);
5740 #ifndef RTE_ETHDEV_TX_PREPARE_NOOP
5742 static inline uint16_t
5744 struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
5746 struct rte_eth_fp_ops *p;
5749 #ifdef RTE_ETHDEV_DEBUG_TX
5750 if (port_id >= RTE_MAX_ETHPORTS ||
5751 queue_id >= RTE_MAX_QUEUES_PER_PORT) {
5753 "Invalid port_id=%u or queue_id=%u\n",
5761 p = &rte_eth_fp_ops[port_id];
5762 qd = p->txq.data[queue_id];
5764 #ifdef RTE_ETHDEV_DEBUG_TX
5766 RTE_ETHDEV_LOG(ERR,
"Invalid Tx port_id=%u\n", port_id);
5771 RTE_ETHDEV_LOG(ERR,
"Invalid Tx queue_id=%u for port_id=%u\n",
5778 if (!p->tx_pkt_prepare)
5781 return p->tx_pkt_prepare(qd, tx_pkts, nb_pkts);
5795 static inline uint16_t
5827 static inline uint16_t
5832 uint16_t to_send = buffer->
length;
5843 buffer->error_callback(&buffer->
pkts[sent],
5844 (uint16_t)(to_send - sent),
5845 buffer->error_userdata);
int rte_eth_dev_stop(uint16_t port_id)
struct rte_eth_vmdq_dcb_tx_conf vmdq_dcb_tx_conf
int rte_eth_dev_priority_flow_ctrl_set(uint16_t port_id, struct rte_eth_pfc_conf *pfc_conf)
int rte_eth_promiscuous_disable(uint16_t port_id)
__extension__ uint32_t multi_pools
int rte_eth_rx_burst_mode_get(uint16_t port_id, uint16_t queue_id, struct rte_eth_burst_mode *mode)
struct rte_eth_dev_portconf default_rxportconf
#define __rte_always_inline
#define RTE_ETH_DCB_NUM_USER_PRIORITIES
uint16_t rte_eth_dev_count_avail(void)
int rte_eth_timesync_write_time(uint16_t port_id, const struct timespec *time)
char info[RTE_ETH_BURST_MODE_INFO_SIZE]
const uint32_t * dev_flags
int rte_eth_dev_get_reg_info(uint16_t port_id, struct rte_dev_reg_info *info)
int rte_eth_timesync_read_time(uint16_t port_id, struct timespec *time)
struct rte_eth_rxseg_capa rx_seg_capa
uint64_t rte_eth_find_next_owned_by(uint16_t port_id, const uint64_t owner_id)
#define __rte_cache_min_aligned
int rte_eth_dev_configure(uint16_t port_id, uint16_t nb_rx_queue, uint16_t nb_tx_queue, const struct rte_eth_conf *eth_conf)
int rte_eth_dev_get_name_by_port(uint16_t port_id, char *name)
static uint16_t rte_eth_tx_prepare(uint16_t port_id, uint16_t queue_id, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
struct rte_device * device
struct rte_eth_vmdq_tx_conf vmdq_tx_conf
const struct rte_eth_rxtx_callback * rte_eth_add_rx_callback(uint16_t port_id, uint16_t queue_id, rte_rx_callback_fn fn, void *user_param)
uint64_t q_errors[RTE_ETHDEV_QUEUE_STAT_CNTRS]
__rte_experimental int rte_eth_dev_owner_new(uint64_t *owner_id)
__rte_experimental int rte_eth_dev_owner_unset(const uint16_t port_id, const uint64_t owner_id)
struct rte_eth_thresh rx_thresh
uint16_t rte_eth_find_next(uint16_t port_id)
int rte_eth_dev_set_vlan_pvid(uint16_t port_id, uint16_t pvid, int on)
int rte_eth_led_off(uint16_t port_id)
int rte_eth_dev_udp_tunnel_port_delete(uint16_t port_id, struct rte_eth_udp_tunnel *tunnel_udp)
static int rte_eth_rx_descriptor_status(uint16_t port_id, uint16_t queue_id, uint16_t offset)
struct rte_eth_fdir_flex_conf flex_conf
__rte_experimental int rte_eth_dev_hairpin_capability_get(uint16_t port_id, struct rte_eth_hairpin_cap *cap)
struct rte_eth_vmdq_dcb_conf::@145 pool_map[RTE_ETH_VMDQ_MAX_VLAN_FILTERS]
int rte_eth_dev_rss_reta_update(uint16_t port_id, struct rte_eth_rss_reta_entry64 *reta_conf, uint16_t reta_size)
int rte_eth_set_queue_rate_limit(uint16_t port_id, uint16_t queue_idx, uint16_t tx_rate)
int rte_eth_dev_rss_hash_update(uint16_t port_id, struct rte_eth_rss_conf *rss_conf)
__rte_experimental int rte_eth_fec_set(uint16_t port_id, uint32_t fec_capa)
uint64_t rx_queue_offload_capa
int rte_eth_xstats_get(uint16_t port_id, struct rte_eth_xstat *xstats, unsigned int n)
__rte_experimental int rte_eth_read_clock(uint16_t port_id, uint64_t *clock)
int rte_eth_iterator_init(struct rte_dev_iterator *iter, const char *devargs)
int rte_eth_dev_rx_intr_ctl_q(uint16_t port_id, uint16_t queue_id, int epfd, int op, void *data)
int rte_eth_remove_rx_callback(uint16_t port_id, uint16_t queue_id, const struct rte_eth_rxtx_callback *user_cb)
enum rte_eth_tx_mq_mode mq_mode
int rte_eth_dev_uc_all_hash_table_set(uint16_t port_id, uint8_t on)
uint64_t tx_queue_offload_capa
uint8_t enable_default_pool
uint32_t max_hash_mac_addrs
int rte_eth_dev_rx_intr_ctl_q_get_fd(uint16_t port_id, uint16_t queue_id)
uint16_t rte_eth_find_next_sibling(uint16_t port_id_start, uint16_t ref_port_id)
uint64_t q_obytes[RTE_ETHDEV_QUEUE_STAT_CNTRS]
int rte_eth_dev_get_eeprom_length(uint16_t port_id)
struct rte_eth_rss_conf rss_conf
int rte_eth_dev_close(uint16_t port_id)
int rte_eth_dev_rx_intr_enable(uint16_t port_id, uint16_t queue_id)
int rte_eth_dev_set_rx_queue_stats_mapping(uint16_t port_id, uint16_t rx_queue_id, uint8_t stat_idx)
int rte_eth_tx_queue_info_get(uint16_t port_id, uint16_t queue_id, struct rte_eth_txq_info *qinfo)
__rte_experimental int rte_eth_dev_get_module_eeprom(uint16_t port_id, struct rte_dev_eeprom_info *info)
uint32_t dcb_capability_en
uint64_t q_ibytes[RTE_ETHDEV_QUEUE_STAT_CNTRS]
__rte_experimental int rte_eth_dev_conf_get(uint16_t port_id, struct rte_eth_conf *dev_conf)
struct rte_eth_switch_info switch_info
int rte_eth_dev_flow_ctrl_get(uint16_t port_id, struct rte_eth_fc_conf *fc_conf)
int rte_eth_dev_callback_unregister(uint16_t port_id, enum rte_eth_event_type event, rte_eth_dev_cb_fn cb_fn, void *cb_arg)
enum rte_eth_fdir_pballoc_type pballoc
int rte_eth_dev_rx_queue_stop(uint16_t port_id, uint16_t rx_queue_id)
int rte_eth_dev_pool_ops_supported(uint16_t port_id, const char *pool)
int rte_eth_dev_set_link_up(uint16_t port_id)
__rte_experimental int rte_eth_rx_metadata_negotiate(uint16_t port_id, uint64_t *features)
int rte_eth_timesync_read_rx_timestamp(uint16_t port_id, struct timespec *timestamp, uint32_t flags)
struct rte_eth_thresh tx_thresh
struct rte_eth_desc_lim rx_desc_lim
int rte_eth_dev_get_vlan_offload(uint16_t port_id)
__rte_experimental int rte_eth_dev_owner_set(const uint16_t port_id, const struct rte_eth_dev_owner *owner)
int rte_eth_tx_queue_setup(uint16_t port_id, uint16_t tx_queue_id, uint16_t nb_tx_desc, unsigned int socket_id, const struct rte_eth_txconf *tx_conf)
int rte_eth_tx_burst_mode_get(uint16_t port_id, uint16_t queue_id, struct rte_eth_burst_mode *mode)
uint8_t rx_deferred_start
int(* rte_eth_dev_cb_fn)(uint16_t port_id, enum rte_eth_event_type event, void *cb_arg, void *ret_param)
struct rte_eth_rxmode rxmode
uint64_t q_ipackets[RTE_ETHDEV_QUEUE_STAT_CNTRS]
enum rte_eth_nb_pools nb_queue_pools
#define RTE_ETH_MQ_RX_RSS_FLAG
struct rte_eth_txconf conf
uint32_t rte_eth_speed_bitflag(uint32_t speed, int duplex)
#define RTE_ETH_XSTATS_NAME_SIZE
int rte_eth_dev_rss_hash_conf_get(uint16_t port_id, struct rte_eth_rss_conf *rss_conf)
__rte_experimental int rte_eth_macaddrs_get(uint16_t port_id, struct rte_ether_addr *ma, unsigned int num)
struct rte_eth_desc_lim tx_desc_lim
int rte_eth_timesync_disable(uint16_t port_id)
int rte_eth_dev_default_mac_addr_set(uint16_t port_id, struct rte_ether_addr *mac_addr)
__rte_experimental int rte_eth_representor_info_get(uint16_t port_id, struct rte_eth_representor_info *info)
void rte_eth_iterator_cleanup(struct rte_dev_iterator *iter)
void * rte_eth_dev_get_sec_ctx(uint16_t port_id)
__rte_experimental int rte_eth_fec_get_capability(uint16_t port_id, struct rte_eth_fec_capa *speed_fec_capa, unsigned int num)
int rte_eth_stats_reset(uint16_t port_id)
int rte_eth_allmulticast_enable(uint16_t port_id)
struct rte_eth_txconf default_txconf
__rte_experimental int rte_eth_get_monitor_addr(uint16_t port_id, uint16_t queue_id, struct rte_power_monitor_cond *pmc)
uint32_t offset_align_log2
int rte_eth_dev_set_ptypes(uint16_t port_id, uint32_t ptype_mask, uint32_t *set_ptypes, unsigned int num)
void rte_eth_tx_buffer_drop_callback(struct rte_mbuf **pkts, uint16_t unsent, void *userdata)
int rte_eth_dev_udp_tunnel_port_add(uint16_t port_id, struct rte_eth_udp_tunnel *tunnel_udp)
struct rte_eth_dcb_rx_conf dcb_rx_conf
struct rte_eth_vmdq_rx_conf vmdq_rx_conf
int rte_eth_timesync_adjust_time(uint16_t port_id, int64_t delta)
uint16_t rte_eth_find_next_of(uint16_t port_id_start, const struct rte_device *parent)
enum rte_eth_rx_mq_mode mq_mode
int rte_eth_dev_callback_register(uint16_t port_id, enum rte_eth_event_type event, rte_eth_dev_cb_fn cb_fn, void *cb_arg)
enum rte_eth_nb_pools nb_queue_pools
struct rte_eth_conf::@147 rx_adv_conf
int rte_eth_dev_tx_queue_stop(uint16_t port_id, uint16_t tx_queue_id)
static uint16_t rte_eth_rx_burst(uint16_t port_id, uint16_t queue_id, struct rte_mbuf **rx_pkts, const uint16_t nb_pkts)
int rte_eth_allmulticast_disable(uint16_t port_id)
__rte_experimental int rte_eth_dev_get_module_info(uint16_t port_id, struct rte_eth_dev_module_info *modinfo)
int rte_eth_dev_set_vlan_strip_on_queue(uint16_t port_id, uint16_t rx_queue_id, int on)
int rte_eth_dev_start(uint16_t port_id)
int rte_eth_dev_reset(uint16_t port_id)
int rte_eth_xstats_get_by_id(uint16_t port_id, const uint64_t *ids, uint64_t *values, unsigned int size)
#define RTE_ETH_MQ_RX_DCB_FLAG
struct rte_eth_dcb_tx_conf dcb_tx_conf
int rte_eth_dev_rx_intr_disable(uint16_t port_id, uint16_t queue_id)
int rte_eth_tx_buffer_set_err_callback(struct rte_eth_dev_tx_buffer *buffer, buffer_tx_error_fn callback, void *userdata)
void rte_eth_tx_buffer_count_callback(struct rte_mbuf **pkts, uint16_t unsent, void *userdata)
uint64_t q_opackets[RTE_ETHDEV_QUEUE_STAT_CNTRS]
int rte_eth_dev_info_get(uint16_t port_id, struct rte_eth_dev_info *dev_info)
int rte_eth_remove_tx_callback(uint16_t port_id, uint16_t queue_id, const struct rte_eth_rxtx_callback *user_cb)
int rte_eth_dev_is_removed(uint16_t port_id)
uint16_t(* rte_tx_callback_fn)(uint16_t port_id, uint16_t queue, struct rte_mbuf *pkts[], uint16_t nb_pkts, void *user_param)
int rte_eth_dev_fw_version_get(uint16_t port_id, char *fw_version, size_t fw_size)
__rte_experimental int rte_eth_link_to_str(char *str, size_t len, const struct rte_eth_link *eth_link)
int rte_eth_dev_adjust_nb_rx_tx_desc(uint16_t port_id, uint16_t *nb_rx_desc, uint16_t *nb_tx_desc)
int rte_eth_dev_mac_addr_remove(uint16_t port_id, struct rte_ether_addr *mac_addr)
int rte_eth_dev_mac_addr_add(uint16_t port_id, struct rte_ether_addr *mac_addr, uint32_t pool)
int rte_eth_dev_tx_queue_start(uint16_t port_id, uint16_t tx_queue_id)
int rte_eth_xstats_reset(uint16_t port_id)
#define RTE_ETH_MQ_RX_VMDQ_FLAG
__rte_experimental int rte_eth_hairpin_get_peer_ports(uint16_t port_id, uint16_t *peer_ports, size_t len, uint32_t direction)
int rte_eth_xstats_get_id_by_name(uint16_t port_id, const char *xstat_name, uint64_t *id)
int rte_eth_dev_get_port_by_name(const char *name, uint16_t *port_id)
__extension__ uint8_t hw_vlan_insert_pvid
const struct rte_eth_rxtx_callback * rte_eth_add_tx_callback(uint16_t port_id, uint16_t queue_id, rte_tx_callback_fn fn, void *user_param)
uint64_t flow_type_rss_offloads
#define RTE_ETH_VMDQ_MAX_VLAN_FILTERS
uint16_t rte_eth_dev_count_total(void)
int rte_eth_promiscuous_enable(uint16_t port_id)
int rte_eth_dev_rx_intr_ctl(uint16_t port_id, int epfd, int op, void *data)
union rte_eth_rxseg * rx_seg
struct rte_eth_dev_portconf default_txportconf
const char * rte_eth_dev_tx_offload_name(uint64_t offload)
__rte_experimental int rte_eth_fec_get(uint16_t port_id, uint32_t *fec_capa)
int rte_eth_link_get(uint16_t port_id, struct rte_eth_link *link)
union rte_eth_conf::@148 tx_adv_conf
static __rte_always_inline uint16_t rte_eth_tx_buffer(uint16_t port_id, uint16_t queue_id, struct rte_eth_dev_tx_buffer *buffer, struct rte_mbuf *tx_pkt)
__extension__ uint8_t hw_vlan_reject_untagged
int rte_eth_dev_set_mc_addr_list(uint16_t port_id, struct rte_ether_addr *mc_addr_set, uint32_t nb_mc_addr)
rte_eth_fdir_pballoc_type
int rte_eth_dev_get_dcb_info(uint16_t port_id, struct rte_eth_dcb_info *dcb_info)
rte_eth_event_ipsec_subtype
struct rte_eth_intr_conf intr_conf
int rte_eth_dev_set_tx_queue_stats_mapping(uint16_t port_id, uint16_t tx_queue_id, uint8_t stat_idx)
int rte_eth_dev_set_eeprom(uint16_t port_id, struct rte_dev_eeprom_info *info)
__rte_experimental const char * rte_eth_link_speed_to_str(uint32_t link_speed)
__rte_experimental int rte_eth_dev_owner_get(const uint16_t port_id, struct rte_eth_dev_owner *owner)
static int rte_eth_rx_queue_count(uint16_t port_id, uint16_t queue_id)
int rte_eth_rx_queue_info_get(uint16_t port_id, uint16_t queue_id, struct rte_eth_rxq_info *qinfo)
int rte_eth_dev_socket_id(uint16_t port_id)
uint8_t enable_default_pool
__extension__ struct rte_eth_link __rte_aligned(8)
int rte_eth_dev_vlan_filter(uint16_t port_id, uint16_t vlan_id, int on)
int rte_eth_link_get_nowait(uint16_t port_id, struct rte_eth_link *link)
int rte_eth_dev_set_mtu(uint16_t port_id, uint16_t mtu)
int rte_eth_dev_set_vlan_ether_type(uint16_t port_id, enum rte_vlan_type vlan_type, uint16_t tag_type)
int rte_eth_xstats_get_names_by_id(uint16_t port_id, struct rte_eth_xstat_name *xstats_names, unsigned int size, uint64_t *ids)
__rte_experimental const char * rte_eth_dev_capability_name(uint64_t capability)
__rte_experimental int rte_eth_rx_hairpin_queue_setup(uint16_t port_id, uint16_t rx_queue_id, uint16_t nb_rx_desc, const struct rte_eth_hairpin_conf *conf)
static uint64_t rte_eth_rss_hf_refine(uint64_t rss_hf)
__rte_experimental int rte_eth_hairpin_bind(uint16_t tx_port, uint16_t rx_port)
int rte_eth_dev_uc_hash_table_set(uint16_t port_id, struct rte_ether_addr *addr, uint8_t on)
int rte_eth_dev_rss_reta_query(uint16_t port_id, struct rte_eth_rss_reta_entry64 *reta_conf, uint16_t reta_size)
int rte_eth_promiscuous_get(uint16_t port_id)
struct rte_eth_fdir_conf fdir_conf
int rte_eth_led_on(uint16_t port_id)
int rte_eth_timesync_read_tx_timestamp(uint16_t port_id, struct timespec *timestamp)
struct rte_eth_vmdq_rx_conf::@146 pool_map[RTE_ETH_VMDQ_MAX_VLAN_FILTERS]
__rte_experimental int rte_eth_dev_owner_delete(const uint64_t owner_id)
int rte_eth_dev_get_supported_ptypes(uint16_t port_id, uint32_t ptype_mask, uint32_t *ptypes, int num)
__extension__ uint8_t hw_vlan_reject_tagged
int rte_eth_stats_get(uint16_t port_id, struct rte_eth_stats *stats)
__rte_experimental int rte_eth_tx_hairpin_queue_setup(uint16_t port_id, uint16_t tx_queue_id, uint16_t nb_tx_desc, const struct rte_eth_hairpin_conf *conf)
uint8_t mac_ctrl_frame_fwd
uint16_t(* rte_rx_callback_fn)(uint16_t port_id, uint16_t queue, struct rte_mbuf *pkts[], uint16_t nb_pkts, uint16_t max_pkts, void *user_param)
enum rte_eth_fc_mode mode
int rte_eth_dev_get_mtu(uint16_t port_id, uint16_t *mtu)
struct rte_eth_vmdq_dcb_conf vmdq_dcb_conf
uint8_t dcb_tc[RTE_ETH_DCB_NUM_USER_PRIORITIES]
uint8_t tx_deferred_start
int rte_eth_tx_buffer_init(struct rte_eth_dev_tx_buffer *buffer, uint16_t size)
uint32_t max_lro_pkt_size
int rte_eth_xstats_get_names(uint16_t port_id, struct rte_eth_xstat_name *xstats_names, unsigned int size)
struct rte_eth_fc_conf fc
const struct rte_eth_rxtx_callback * rte_eth_add_first_rx_callback(uint16_t port_id, uint16_t queue_id, rte_rx_callback_fn fn, void *user_param)
int rte_eth_tx_done_cleanup(uint16_t port_id, uint16_t queue_id, uint32_t free_cnt)
int rte_eth_dev_set_vlan_offload(uint16_t port_id, int offload_mask)
struct rte_eth_txmode txmode
int rte_eth_allmulticast_get(uint16_t port_id)
int rte_eth_dev_is_valid_port(uint16_t port_id)
int rte_eth_macaddr_get(uint16_t port_id, struct rte_ether_addr *mac_addr)
uint32_t max_lro_pkt_size
int rte_eth_timesync_enable(uint16_t port_id)
struct rte_eth_rxconf default_rxconf
static uint16_t rte_eth_tx_burst(uint16_t port_id, uint16_t queue_id, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
int rte_eth_dev_rx_queue_start(uint16_t port_id, uint16_t rx_queue_id)
int rte_eth_dev_set_link_down(uint16_t port_id)
int rte_eth_dev_flow_ctrl_set(uint16_t port_id, struct rte_eth_fc_conf *fc_conf)
uint16_t rte_eth_iterator_next(struct rte_dev_iterator *iter)
__rte_experimental int rte_eth_hairpin_unbind(uint16_t tx_port, uint16_t rx_port)
enum rte_fdir_status_mode status
int rte_eth_dev_get_eeprom(uint16_t port_id, struct rte_dev_eeprom_info *info)
const char * rte_eth_dev_rx_offload_name(uint64_t offload)
static uint16_t rte_eth_tx_buffer_flush(uint16_t port_id, uint16_t queue_id, struct rte_eth_dev_tx_buffer *buffer)
int rte_eth_rx_queue_setup(uint16_t port_id, uint16_t rx_queue_id, uint16_t nb_rx_desc, unsigned int socket_id, const struct rte_eth_rxconf *rx_conf, struct rte_mempool *mb_pool)